1. Field of the Invention
The present invention relates to memory systems for computers, and more particularly to the design of a memory interface that automatically adjusts the timing between data and clock signals received from a memory during a read operation.
2. Related Art
As processor speeds continue to increase, memory systems are under increasing pressure to provide data at faster rates. This has recently led to the development of new memory system designs. Memory latencies have been dramatically decreased by using page mode and extended data out (EDO) memory designs, which achieve a high burst rate and low latencies within a single page of memory. Another recent innovation is to incorporate a synchronous clocked interface into a memory chip, thereby allowing data from within the same page of memory to be clocked out of the memory in a continuous stream. Such memory chips, with clocked interfaces are known as synchronous random access memories.
Recently, standards such as Rambus, SyncLink and DDR have been developed to govern the transfer of data between memory and processor using such clocked interfaces. SyncLink, which will be known as IEEE Standard 1596.7, specifies an architecture that supports a 64 M-bit memory with a data transfer rate of 1.6 gigabytes per second. SyncLink packetizes and pipelines the address, command and timing signals, and adds features that significantly increase data bus speed, thereby providing fast memory accesses without losing the ability to move quickly from row to row or to obtain bursts of data. DDR is an acronym for Double Data Rate SDRAM; SDRAM is an acronym for Synchronous Dynamic Random Access Memory.
During read operations, SyncLink (and DDR) memories return a data clock signal (or data strobe) along with the data, and this data clock signal is used to clock the data into the processor (or into a memory controller attached to the processor). This differs from conventional memory systems, which rely on the system clock to latch data received during read operations.
Designing an interface that receives a data clock signal from a SyncLink memory during a read operation presents challenges because a certain amount of skew typically arises between the data signal and the data clock signal. If this skew is large enough, a clock edge, which is used to latch the data signal, can move from the center of the "data eye" of the data signal into a transitional region or into another data eye. This may cause spurious data to be latched during read operations. To remedy this problem, the SyncLink standard allows the timing between the data signal and the data clock signal to be aligned by adjusting an internal delay counter in within a SyncLink memory device. However, corresponding external support circuitry does not presently exist to perform this alignment.
What is needed is a system that measures skew between a data clock signal and a data signal received from a memory during a read operation and that adjusts the temporal alignment between these signals if necessary.